Ultra-high-speed wireless communication technologies, typified by millimeter-wave wireless communication using the 60 GHz band, are being researched and developed in which data rates exceeding one gigabit per second have been realized. When data rates exceed one gigabit per second, various challenges arise in wireless communication transmitters and receivers. In typical wireless communication, data is sent and received by the transmitter and receiver at different frequencies. This is due to the accuracy of the oscillator generating the clock supplied to the digital circuits in the transmitter and the receiver, circuit mounting conditions, and temperature conditions.
When the symbol timing for the baseband signals of the transmitter and the receiver have different frequencies, sampling is performed in the center of the eye pattern immediately after synchronization, but the sampling position gradually shifts forward or backward in accordance with the frequency offset. Eventually, the boundary of the eye pattern is reached, symbols cannot be accurately determined, and data restoration fails. Therefore, there is a need to compensate for these frequency offsets.
High-speed compensation must be performed to compensate for frequency offsets in ultra-high-speed communication, and compensation must be performed on each packet when packet communication is expected. One technique for restoring the symbol time of a transmitter is to use an analog PLL (phase synchronization circuit). However, several thousand clocks occur before synchronization with the frequency of the received signals, and high-speed synchronization is not possible. Also, when sampling is performed using an analog-to-digital converter (ADC), the symbol time is very short, and oversampling can be performed at most only several times.
In the technique disclosed in Patent Literature 1, resampling is performed on received signals at the desired sample time using a digital resampling circuit. The resampling circuit is realized by performing interpolation and decimation at the appropriate ratio using a polyphase filter. Instead of directly tinkering with the sampling frequency of the ADC, resampling is realized using a digital circuit. Also, frequency offset compensation and equalization such as inter-symbol interference (ISI) cancellation are performed using filters in a subsequent stage, and data decimation is performed after this to obtain the original symbol rate. This method takes a long time to determine the coefficient of the resampling circuit, and the circuit configuration is large.